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Integrated Circuit Systems, Inc.
ICS94222
Advance Information
Programmable System Frequency Generator for PII/IIITM
Recommended Application: BX, Appollo Pro 133 type of chip set. Output Features: * 3 - CPUs @2.5V, up to 166MHz. * 17 - SDRAM @ 3.3V, up to 166MHz. * 7 - PCI @3.3V * 2 - IOAPIC @ 2.5V * 1 - 48MHz, @3.3V fixed. * 1 - 24MHz @ 3.3V * 2 - REF @3.3V, 14.318MHz. Features: * Programmable ouput frequency. * Programmable ouput rise/fall time. * Programmable PCI_F and PCICLK skew. * Spread spectrum for EMI control typically by 7dB to 8dB, with programmable spread percentage. * Watchdog timer technology to reset system if over-clocking causes malfunction. * Uses external 14.318MHz crystal. * FS pins for frequency select Key Specifications: * CPU - CPU: <175ps * SDRAM - SDRAM: <500ps * PCI - PCI: <500ps * CPU-SDRAM: <500ps * CPU(early)-PCI: Min=1.0ns, Typ=2.0ns, Max=4.0ns
Pin Configuration
AVDD *FS2/REF1 *PCI_STOP#/REF0 GND X1 X2 VDD *MODE/PCICLK_F *FS3/PCICLK0 GND PCICLK1 PCICLK2 PCICLK3 PCICLK4 VDD PCICLK5 BUFFERIN SDRAM11 SDRAM10 VDD SDRAM9 SDRAM8 GND SDRAM15 SDRAM14 GND SDATA SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDDL IOAPIC0 IOAPIC_F GND CPUCLK_F CPUCLK0 VDDL CPUCLK1 GND CLK_STOP* SDRAM_F VDDSDR SDRAM0 SDRAM1 GND SDRAM2 SDRAM3 SDRAM4 SDRAM5 VDD SDRAM6 SDRAM7 GND SDRAM12 SDRAM13 AVDD48 24MHz/FS0* 1 48MHz/FSI*
56-Pin SSOP
* Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
Functionality Block Diagram
PLL2
/2
ICS94222
CPU (MHz) 80.00 75.00 83.31 66.9 103.00 112.01 68.01 100.7 120.00 114.99 109.99 105.00 140.00 150.00 124.00 133.9
48MHz 24MHz IOAPIC_F
FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
X1 X2
XTAL OSC
STOP
IOAPIC0
2
REF [1:0] CPUCLK_F CPUCLK (1:0)
PLL1 Spread Spectrum FS (3:0) MODE
POR LATCH
PCI CLOCK DIVDER
1
STOP
STOP
6
PCICLK (5:0) PCICLK_F
CLK_STOP# PCI_STOP# SCLK SDATA BUFFERIN Control Logic Config. Reg.
STOP
16
SDRAM (15:0) SDRAM_F
PCICLK (MHz) 40.00 37.50 41.65 33.45 34.33 37.34 34.01 33.57 40.00 38.33 36.66 35.00 35.00 37.50 31.00 33.25
94222 Rev - 5/10/01 This document is confidential and should not be released without written consents from ICS.
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice.
ICS94222
Advance Information
Pin Configuration
PIN NUMBER 1 2 P I N NA M E AVDD REF1 FS21 REF0 P C I _ S TO P # 1 TYPE PWR OUT IN OUT IN PWR IN OUT PWR OUT IN IN OUT OUT IN IN IN OUT IN OUT IN PWR DESCRIPTION Analog power supply 3.3V 14.318 MHz reference clock output L a t c h e d f r e q u e n cy s e l e c t i n p u t . H a s p u l l - u p t o V D D 14.318MHz reference clock output Halts PCICLK [5:1] at logic "0" level when low. (in mobile, MODE=0) Ground. 14.318MHz input. Has internal load cap, (nominal 33pF). Crystal output. Has internal load cap (33pF) and feedback resistor to X1 Nominal 3.3V power supply, see power groups for function. F r e e r u n n i n g B U S c l o c k n o t a f e c t e d b y P C I _ S TO P # Latched input for MODE select. Converts pin 3 to PCI_STOP# when low for power management. Latched frequency select input, pull-down F r e e r u n n i n g B U S c l o c k n o t a f e c t e d b y P C I _ S TO P # PCI Clock Outputs. Input for Buffers Serial data in for serial config port. (I2C) Clock input for serial config port. (I2C) 24MHz clock output for Super I/O or FD. L a t c h e d f r e q u e n cy s e l e c t i n p u t . H a s p u l l - u p t o V D D 48MHz clock output for USB, 2X strength. L a t c h e d f r e q u e n cy s e l e c t i n p u t . H a s p u l l - u p t o V D D Analog power supply 3.3V
3
4, 10, 23, 26, 34, 42, GND 48, 53 5 6 7, 15, 20, 37, 45 8 X1 X2 VDD PCICLK_F MODE1 FS31 PCICLK0 PCICLK (5:1) BU F F E R I N SDATA SCLK 24MHz 30 FS0 29 31 24, 25, 32, 33, 18, 19, 21, 22, 35, 36, 38, 39, 40, 41, 43, 44 46 47 50, 56 55 49, 51 52 54
1
9 16, 14, 13, 12, 11 17 27 28
48MHz FS11 AVDD48
SDRAM (15:0)
OUT
SDRAM clocks
SDRAM_F C L K _ S TO P # VDDL I OA P I C 0 CPUCLK (1:0) CPUCLK_F I OA P I C _ F
OUT IN PWR OUT OUT OUT OUT
Free running SDRAM clock Not affected by CPU_STOP# Halts CPUCLKs, IOAPIC0, SDRAMs clocks at logic "0" level when low. CPU and IOAPIC clock buffer power supply, 2.5V nominal. IOAPIC clock output. (14.318 MHz) Poweredby VDDL CPU Output clocks. Powered by VDDL (60 or 66.6MHz) Free running CPU output clock. Not affected ty the CLK_STOP#. Freerunning IOAPIC clock output. Not affected by the CLK_STOP# (14.31818 MHz) Powered by VDDL
Notes: 1: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low.
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2
ICS94222
Advance Information
General Description
The ICS94222 is a single chip clock solution for desktop designs using the BX/Apollo Pro133/ALI 1631 style chipset. It provides all necessary clock signals for such a system. The ICS94222 belongs to ICS new generation of programmable system clock generators. It employs serial programming I2C interface as a vehicle for changing output functions, changing output frequency, configuring output strength, configuring output to output skew, changing spread spectrum amount, changing group divider ratio and dis/enabling individual clocks. This device also has ICS propriety 'Watchdog Timer' technology which will reset the frequency to a safe setting if the system become unstable from over clocking.
Mode Pin - Power Management Input Control
MODE (Latched Input) 0 1 Pin 3 PCI_STOP# (Input) REF0 (Output)
Power Groups
AVDD48 = 48MHz, Fixed PLL AVDD = CPU PLL, XTAL
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3
ICS94222
Advance Information
General I2C serial interface information for the ICS94222 How to Write:
* * * * * * * * Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending Byte 0 through Byte 20 (see Note) * ICS clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends Byte 0 through byte 8 (default) ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). * Controller (host) will need to acknowledge each byte * Controller (host) will send a stop bit * * * * * * *
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ACK Dummy Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Byte 6 ACK ICS (Slave/Receiver)
How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK
ACK Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Byte 6 ACK If 7H has been written to B6 ACK Byte 7
Byte 18 ACK Byte 19 ACK Byte 20 ACK Stop Bit
*See notes on the following page.
This document is confidential and should not be released without written consent from ICS.
If 12H has been written to B6 ACK If 13H has been written to B6 ACK If 14H has been written to B6 ACK Stop Bit
Byte18 Byte 19 Byte 20
4
ICS94222
Advance Information Brief I2C registers description for ICS94222 Programmable System Frequency Generator
Register N ame Functionality & Frequency Select Register Output Control Registers Vendor ID & Revision ID Registers Byte 0 Description Output frequency, hardware / I C frequency select, spread spectrum & output enable control register. Active / inactive output control registers/latch inputs read back. Byte 11 bit[7:4] is ICS vendor id - 1001. Other bits in this register designate device revision ID of this part. Writing to this register will configure byte count and how many byte w ill be read back. Do not write 00 H to this byte. Watchdog enable, watchdog status and programmable 'safe' frequency' can be configured in this register. This bit select w hether the output frequency is control by hardware/byte 0 configurations or byte 11&12 programming. Writing to this register will configure the number of seconds for the watchdog timer to reset. These registers control the dividers ratio into the phase detector and thus control the V CO output frequency. These registers control the spread percentage amount. Increment or decrement the group skew amount as compared to the initial skew . These registers will control the output rise and fall time.
2
PW D Default See individual byte description See individual byte description See individual byte description
1-6
7
Byte Count Read Back Register
8
08 H
Watchdog Control Registers 9 Bit [6:0]
000,0000
VCO Control Selection Bit
9 Bit [7]
0
Watchdog Timer Count Register
10
10 H
VCO Frequency Control Registers Spread Spectrum Control Registers Group Skews Control Registers Output Rise/Fall Time Select Registers
11-12
Depended on hardware/byte 0 configuration Depended on hardware/byte 0 configuration See individual byte description See individual byte description
13-14
15-16 17-20
Notes:
1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Readback will support standard SMBUS controller protocol. The number of bytes to readback is defined by writing to byte 8. When writing to byte 11 - 12, and byte 13 - 14, they must be written as a set. If for example, only byte 14 is written but not 15, neither byte 14 or 15 will load into the receiver. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only Block-Writes from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
2. 3. 4. 5. 6.
7.
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5
ICS94222
Advance Information
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Description CPUCLK PCICLK Bit2 Bit7 Bit6 Bit5 Bit4 MHz MHz 0 0 0 0 0 80.00 40.00 0 0 0 0 1 75.00 37.50 0 0 0 1 0 83.31 41.65 0 0 0 1 1 66.9 33.45 0 0 1 0 0 103.00 34.33 0 0 1 0 1 112.01 37.34 0 0 1 1 0 68.01 34.01 0 0 1 1 1 100.7 33.57 0 1 0 0 0 120.00 40.00 0 1 0 0 1 114.99 38.33 0 1 0 1 0 109.99 36.66 0 1 0 1 1 105.00 35.00 0 1 1 0 0 140.00 35.00 0 1 1 0 1 150.00 37.50 0 1 1 1 0 124.00 31.00 0 1 1 1 1 133.9 33.25 1 0 0 0 0 135.00 33.75 1 0 0 0 1 129.99 32.50 1 0 0 1 0 126.00 31.50 1 0 0 1 1 118.00 39.33 1 0 1 0 0 115.98 38.66 1 0 1 0 1 95.00 31.67 1 0 1 1 0 90.00 30.00 1 0 1 1 1 85.01 28.34 1 1 0 0 0 166.00 41.50 1 1 0 0 1 160.01 40.00 1 1 0 1 0 154.99 38.75 1 1 0 1 1 147.95 36.99 1 1 1 0 0 145.98 36.50 1 1 1 0 1 143.98 35.99 1 1 1 1 0 141.99 35.50 1 1 1 1 1 138.01 34.50 0 - Frequency is selected by hardware select, latched inputs 1 - Frequency is selected by Bit 2, 7:4 0 - Normal 1 - Spread Spectrum Enabled 0.25% (Center Spread) 0 - Running 1- Tristate all outputs
PWD
Bit 2,7, 6:4
XXXX Note1
Bit 3 Bit 1 Bit 0
0 1 0
Note 1. Default at Power-up will be for latched logic inputs to define frequency as displayed by Bit 3. Note: PWD = Power-Up Default
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6
ICS94222
Advance Information
Byte 1: CPU, Active/Inactive Register (1= enable, 0 = disable)
Byte 2: PCI, Active/Inactive Register (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# 46 49 51 52
PWD 1 1 1 1 1 1 1 1
DESCRIPTION R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d SDRAM_F (Act/Inact) CPUCLK1 (Act/Inact) CPUCLK0 (Act/Inact) CPUCLK_F (Act/Inact)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# 8 16 14 13 12 11 9
PWD 1 1 1 1 1 1 1 1
DESCRIPTION R e s e r ve d PCICLKF (Act/Inact) PCICLK5 (Act/Inact) PCICLK4 (Act/Inact) PCICLK3 (Act/Inact) PCICLK2 (Act/Inact) PCICLK1 (Act/Inact) PCICLK0 (Act/Inact)
Byte 3: SDRAM, Active/Inactive Register (1= enable, 0 = disable)
Byte 4: Reserved , Active/Inactive Register (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# 29 30 33, 32, 25, 24 22, 21, 19, 18 39, 38, 36, 35 44, 43, 41, 40
PWD 1 1 1 1 1 1 1 1
DESCRIPTION R e s e r ve d R e s e r ve d 48MHz (Act/Inact) 24MHz (Act/Inact) SDRAM (15:12) (Act/Inact) SDRAM (11:8) (Act/Inact) SDRAM (7:4) (Act/Inact) SDRAM (3:0) (Act/Inact)
BIT PIN# PWD Bit 7 X Bit 6 1 Bit 5 1 Bit 4 X Bit 3 1 Bit 2 1 Bit 1 X Bit 0 1
DESCRIPTION Latched FS0# R e s e r ve d R e s e r ve d Latched FS1# R e s e r ve d R e s e r ve d Latched FS3# R e s e r ve d
Byte 6: Peripheral , Active/Inactive Register (1= enable, 0 = disable)
Byte 5: Peripheral , Active/Inactive Register (1= enable, 0 = disable)
BIT PIN# PWD Bit 7 1 Bit 6 X Bit 5 54 1 Bit 4 55 1 Bit 3 1 Bit 2 1 Bit 1 2 1 Bit 0 3 1
DESCRIPTION R e s e r ve d Latched FS2# IOAPIC_F (Act/Inact) IOAPIC0 (Act/Inact) R e s e r ve d R e s e r ve d REF1 (Act/Inact) REF0 (Act/Inact)
BIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PIN# -
PWD 0 0 0 0 0 1 1 0
DESCRIPTION R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e )
Note: This is an unused register writing to this register will not affect device performance or functinality.
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. 2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.
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7
ICS94222
Advance Information
Byte 7: Vendor ID and Revision ID Register
Byte 8: Byte Count and Read Back Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD 0 0 1 X X X X X
Description Vendor ID Vendor ID Vendor ID Revision ID Revision ID Revision ID Revision ID Revision ID
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD 0 0 0 0 1 0 0 0
Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Byte 9: VCO Control Selection Bit & Watchdog Timer Control Register
Byte 10: Watchdog Timer Count Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD 0 0 0 0 0 0 0 0
Description 0=Hw/B0 freq / 1=B14&15 freq WD Enable 0=disable / 1=enable WD Status 0=normal / 1=alarm WD Safe Frequency, Byte 0 bit 2 WD Safe Frequency, FS3 WD Safe Frequency, FS2 WD Safe Frequency, FS1 WD Safe Frequency, FS0
Note: FS values in bit [0:4] will correspond to Byte 0 FS values. Default safe frequency is same as 00000 entry in byte0.
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD 0 0 0 1 0 0 0 0
Description The decimal representation of these 8 bits correspond to 290ms or 1ms the watchdog timer will wait before it goes to alarm mode and reset the frequency to the safe setting. Default at power up is 16X 290ms = 4.6 seconds.
Byte 11: VCO Frequency Control Register
Byte 12: VCO Frequency Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD X X X X X X X X
Description VCO Divider Bit0 REF Divider Bit6 REF Divider Bit5 REF Divider Bit4 REF Divider Bit3 REF Divider Bit2 REF Divider Bit1 REF Divider Bit0
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD X X X X X X X X
Description VCO Divider Bit8 VCO Divider Bit7 VCO Divider Bit6 VCO Divider Bit5 VCO Divider Bit4 VCO Divider Bit3 VCO Divider Bit2 VCO Divider Bit1
Note: The decimal representation of these 7 bits (Byte 11 [6:0]) + 2 is equal to the REF divider value .
Notes: 1. PWD = Power on Default
Note: The decimal representation of these 9 bits (Byte 12 bit [7:0] & Byte 11 bit [7] ) + 8 is equal to the VCO divider value. For example if VCO divider value of 36 is desired, user need to program 36 - 8 = 28, namely, 0, 00011100 into byte 12 bit & byte 11 bit 7.
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8
ICS94222
Advance Information
Byte 13: Spread Sectrum Control Register
Byte 14: Spread Sectrum Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD X X X X X X X X
Description Spread Spectrum Bit7 Spread Spectrum Bit6 Spread Spectrum Bit5 Spread Spectrum Bit4 Spread Spectrum Bit3 Spread Spectrum Bit2 Spread Spectrum Bit1 Spread Spectrum Bit0
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD X X X X X X X X
Description Reserved Reserved Reserved Spread Spectrum Bit12 Spread Spectrum Bit11 Spread Spectrum Bit10 Spread Spectrum Bi 9 Spread Spectrum Bit8
Note: Please utilize software utility provided by ICS Application Engineering to configure spread spectrum. Incorrect spread percentage may cause system failure.
Note: Please utilize software utility provided by ICS Application Engineering to configure spread spectrum. Incorrect spread percentage may cause system failure.
Byte 15: Output Skew Control
Byte 16: Output Skew Control
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD Description 0 1 PCICLK (5:0) Skew Control 1 0 0 1 PCICLK_F Skew Control 1 0
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD X X X X X X X X
Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Byte 17: Output Rise/Fall Time Select Register
Byte 18: Output Rise/Fall Time Select Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD 1 0 1 0 1 0 1 0
Description CPUCLK_F: Slew Rate Control CPUCLK1: Slew Rate Control SDRAM_F: Slew Rate Control SDRAM (11:0) Slew Rate Control
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD 1 0 1 0 1 0 1 0
Description PCI (4:0) Slew Rate Control PCI_F Slew Rate Control 48MHz: Slew Rate Control 24MHz: Slew Rate Control
Notes: 1. PWD = Power on Default 2. The power on default for byte 13-20 depends on the harware (latch inputs FS[0:4]) or I2C (Byte 0 bit [1:7]) setting. Be sure to read back and re-write the values of these 8 registers when VCO frequency change is desired for the first pass. 3. If Byte 8 bit 7 is driven to "1" meaning programming is intended, Byte 21-24 will lose their default power up value.
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9
ICS94222
Advance Information
Byte 19: Reserved Register Byte 20: Reserved Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD X X X X X X X X
Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD X X X X X X X X
Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Note: Byte 19 and 20 are reserved registers, these are
unused registers writing to these registers will not affect device performance or functinality.
VCO Programming Constrains VCO Frequency ...................... 150MHz to 500MHz VCO Divider Range ................ 8 to 519 REF Divider Range ................. 2 to 129 Phase Detector Stability .......... 0.3536 to 1.4142 Useful Formula VCO Frequency = 14.31818 x VCO/REF divider value Phase Detector Stabiliy = 14.038 x (VCO divider value)-0.5 To program the VCO frequency for over-clocking. 0. Before trying to program our clock manually, consider using ICS provided software utilities for easy programming. 1. Select the frequency you want to over-clock from with the desire gear ratio (i.e. CPU:SDRAM:3V66:PCI ratio) by writing to byte 0, or using initial hardware power up frequency. 2. Write 0001, 1001 (19H) to byte 8 for readback of 21 bytes (byte 0-20). 3. Read back byte 11-20 and copy values in these registers. 4. Re-initialize the write sequence. 5. Write a '1' to byte 9 bit 7 and write to byte 11 & 12 with the desired VCO & REF divider values. 6. Write to byte 13 to 20 with the values you copy from step 3. This maintains the output spread, skew and slew rate. 7. The above procedure is only needed when changing the VCO for the 1st pass. If VCO frequency needed to be changed again, user only needs to write to byte 11 and 12 unless the system is to reboot. Note: 1. User needs to ensure step 3 & 7 is carried out. Systems with wrong spread percentage and/or group to group skew relation programmed into bytes 13-16 could be unstable. Step 3 & 7 assure the correct spread and skew relationship. 2. If VCO, REF divider values or phase detector stability are out of range, the device may fail to function correctly. 3. Follow min and max VCO frequency range provided. Internal PLL could be unstable if VCO frequency is too fast or too slow. Use 14.31818MHz x VCO/REF divider values to calculate the VCO frequency (MHz). 4. ICS recommends users, to utilize the software utility provided by ICS Application Engineering to program the VCO frequency. 5. Spread percent needs to be calculated based on VCO frequency, spread modulation frequency and spreadamount desired. See Application note for software support.
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10
ICS94222
Advance Information
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V GND -0.5 V to VDD +0.5 V 0C to +70C 115C -65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70 C; Supply Voltage VDD, VDDL = 3.3 V +/-5% (unless otherwise stated) PARAMETER SYMBOL CONDITIONS Input High Voltage VIH Input Low Voltage VIL Input High Current IIH VIN = VDD VIN = 0 V; Inputs with no pull-up resistors Input Low Current IIL1 VIN = 0 V; Inputs with pull-up resistors Input Low Current IIL2 Operating IDD3.3OP66 CL = 0 pF; Select @ 66MHz Supply Current IDD3.3OP100 CL = 0 pF; Select @ 100MHz Input frequency Fi VDD = 3.3 V; 1 Input Capacitance CIN Logic Inputs Clk Stabilization 1
1
MIN 2 VSS-0.3 -5 -200
TYP
MAX UNITS VDD+0.3 V 0.8 V 5 A A A 180 mA MHz pF pF ms
12 27
16 5 45 3
CINX TSTAB
X1 & X2 pins From VDD = 3.3 V to 1% target Freq.
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70 C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER Operating Supply Current Skew1
1
SYMBOL IDD2.5OP66 IDD2.5OP100 tCPU-PCI
CONDITIONS CL = 0 pF; Select @ 66.8 MHz CL = 0 pF; Select @ 100 MHz VT = 1.5 V; VTL = 1.25 V
MIN
TYP
1.5
MAX 72 100 4
UNITS mA ns
Guaranteed by design, not 100% tested in production.
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11
ICS94222
Advance Information
Electrical Characteristics - CPUCLK
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter, Cycle-to-cycle Jitter, One Sigma Jitter, Absolute
1
SYMBOL VOH2B VOL2B IOH2B IOL2B tr2B tf2B
1 1
CONDITIONS IOH = -12.0 mA IOL = 12 mA VOH = 1.7 V VOL = 0.7 V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V VT = 1.25 V VT = 1.25 V VT = 1.25 V VT = 1.25 V
MIN 2
TYP
19
MAX UNITS V 0.4 V -19 mA mA 1.6 1.6 ns ns % ps ps ps ps
d t2B1 tsk2B1 tjcyc-cyc2B1 tj1s2B1 tjabs2B1
45
55 175 250 150
-250
+250
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time
1 1 1 1
SYMBOL VOH1 VOL1 IOH1 IOL1 tr1 tf1 dt1 tsk1 tjcyc-cyc2B1 tj1s1 tjabs1
CONDITIONS IOH = -11 mA IOL = 9.4 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 2.4
TYP
25
MAX UNITS V 0.4 V -22 mA mA 2 2 ns ns % ps ps ps ps
Duty Cycle
45
55 500 250 150
Skew Jitter, Cycle-to-cycle Jitter, One Sigma Jitter, Absolute
1 1 1
-500
500
Guaranteed by design, not 100% tested in production.
This document is confidential and should not be released without written consent from ICS.
12
ICS94222
Advance Information
Electrical Characteristics - SDRAM
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Propagation Delay
1 1
SYMBOL VOH3 VOL3 IOH3 IOL3 Tr3 Tf3
1 1
CONDITIONS IOH = -28 mA IOL = 23 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 2.4
TYP
41
MAX UNITS V 0.4 V -54 mA mA 2 2 ns ns % ps ns
Dt3 1 Tsk1 Tprop
45
55 500 5
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - IOAPIC
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time
1 1 1 1
SYMBOL VOH4B VOL4B IOH4B IOL4B Tr4B Tf4B Dt4B Tj1s4B Tjabs4B
CONDITIONS IOH = -12 mA IOL = 12 mA VOH = 1.7 V VOL = 0.7 V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V VT = 1.25 V VT = 1.25 V
MIN 2
TYP
19
MAX UNITS V 0.4 V -19 mA mA 2 2 ns ns % ns ns
Duty Cycle
45 -1
55 0.5 1
Jitter, One Sigma Jitter, Absolute
1
1
Guaranteed by design, not 100% tested in production.
This document is confidential and should not be released without written consent from ICS.
13
ICS94222
Advance Information
Electrical Characteristics - 24MHz, 48MHz, REF
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time
1 1 1 1
SYMBOL VOH5 VOL5 IOH5 IOL5 tr5 tf5 dt5 tj1s5 tjabs5
CONDITIONS IOH = -16 mA IOL = 9 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 2.4
TYP
16
MAX UNITS V 0.4 V -22 mA mA 4 4 ns ns % ns ns
Duty Cycle
45 -1
55 0.5 1
Jitter, One Sigma Jitter, Absolute
1
1
Guaranteed by design, not 100% tested in production.
This document is confidential and should not be released without written consent from ICS.
14
ICS94222
Advance Information
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) on the ICS94222 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad 2K W
Via to VDD
8.2K W Clock trace to load Series Term. Res.
Fig. 1
This document is confidential and should not be released without written consent from ICS.
15
ICS94222
Advance Information
CLK_STOP# Timing Diagram
CLK_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation. CLK_STOP# is synchronized by the ICS94222. The minimum that the CPU clock is enabled (CLK_STOP# high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
INTERNAL CPUCLK PCICLK CLK_STOP# PCI_STOP# (High) IOAPIC
SDRAM CPUCLK CPUCLK _F SDRAM_F
Notes: 1. All timing is referenced to the internal CPU clock. 2. CLK_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPU clocks inside the ICS94222. 3. IOAPIC output is Stopped Glitch Free by CLK_STOP# going low. 4. SDRAM-F output is controlled by Buffer in signal, not affected by the ICS94222 CLK_STOP# signal. SDRAM's are controlled as shown. 5. All other clocks continue to run undisturbed.
This document is confidential and should not be released without written consent from ICS.
16
ICS94222
Advance Information
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS94222. It is used to turn off the PCICLK clocks for low power operation. PCI_STOP# is synchronized by the ICS94222 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP# high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS94222 device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the ICS94222. 3. All other clocks continue to run undisturbed. 4. CPU_STOP# is shown in a high (true) state.
This document is confidential and should not be released without written consent from ICS.
17
ICS94222
Advance Information
0ns
10ns
20ns
30ns
40ns
Cycle Repeats
CPU 66MHz CPU 100MHz CPU 133MHz
SDRAM 100MHz SDRAM 133MHz
3.5V 66MHz PCI 33MHz APIC 33MHz REF 14.318MHz USB 48MHz
Group Offset Waveforms
This document is confidential and should not be released without written consent from ICS.
18
ICS94222
Advance Information
N
c
L
SYMBOL A A1 b c D E E1 e h L N
INDEX AREA
E1
E
12 D h x 45
a
A A1
In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8 VARIATIONS D mm. MIN MAX 18.31 18.55
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
-Ce
b SEATING PLANE .10 (.004) C
N 56
10-0034
D (inch) MIN .720 MAX .730
Reference Doc.: JEDEC Publication 95, MO-118
300 mil SSOP Package
Ordering Information
ICS94222yFT
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type Prefix ICS, AV = Standard Device
This document is confidential and should not be released without written consent from ICS.
19
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice.

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